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?2004 fairchild semiconductor corporation december 2004 fdm606p rev. d2 fdm606p fdm606p p-channel 1.8v logic level power trench ? mosfet general description this p-channel mosfet is produced using fairchild semiconductor?s advanced powertrench process that has been especially tailored to minimize the on-state resistance and yet maintain low gate charge for superior switching performance. these devices are well suited for portable electronics applications. applications ? load switch ? battery charge ? battery disconnect circuits features ? fast switching ?r ds(on) = 0.026 ? (typ), v gs = -4.5v ?r ds(on) = 0.033 ? (typ), v gs = -2.5v ?r ds(on) = 0.052 ? (typ), v gs = -1.8v mosfet maximum ratings t a =25c unless otherwise noted thermal characteristics package marking and ordering information symbol parameter ratings units v dss drain to source voltage -20 v v gs gate to source voltage 8v i d drain current -6.8 a continuous (t c = 25 o c, v gs = - 4.5v) continuous (t c = 100 o c, v gs = - 2.5v) -3.8 a continuous (t c = 100 o c, v gs = -1.8v) -3.0 a pulsed figure 4 p d power dissipation derate above 25c 1.92 15.4 w mw/ o c t j , t stg operating and storage temperature -55 to 150 o c r jc thermal resistance junction to case (note1) 6.0 o c/w r ja thermal resistance junction to ambient (note 2) 65 o c/w r ja thermal resistance junction to ambient (note 3) 208 o c/w device marking device package reel size tape width quantity .06p fdm606p microfet3x2 178 mm 8 mm 3000 1 d s 1 microfet 3x2-8 1 2 3 4 8 7 6 5 1 1
?2004 fairchild semiconductor corporation fdm606p rev. d2 fdm606p electrical characteristics t a = 25c unless otherwise noted off characteristics on characteristics dynamic characteristics switching characteristics (v gs = -4.5v) drain-source diode characteristics notes: 1. r ja is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the s older mounting surface of the center drain pad. r jc is guaranteed by design while r ca is determined by user?s board design. 2. r ja is 65 o c/w (steady state) when mounted on a 1 inch 2 copper pad on fr-4. 3. r ja is 208 o c/w (steady state) when mounted on a minimum pad area. symbol parameter test conditions min typ max units b vdss drain to source breakdown voltage i d = -250 a, v gs = 0v -20 - - v i dss zero gate voltage drain current v ds = -16v v gs = 0v - - -1 a t a = 100 o c - - - 5 i gss gate to source leakage current v gs = 8v - - 100 na v gs(th) gate to source threshold voltage v gs = v ds , i d = -250 a -0.4 -0.9 -1.5 v r ds(on) drain to source on resistance i d = -6.8a, v gs = -4.5v - 0.026 0.030 ? i d = -3.8a, v gs = -2.5v - 0.033 0.038 i d = -3.0a, v gs = -1.8v - 0.052 0.070 c iss input capacitance v ds = -10v, v gs = 0v, f = 1mhz - 2200 - pf c oss output capacitance - 350 - pf c rss reverse transfer capacitance - 160 - pf q g(tot) total gate charge at -4.5v v gs = 0v to -4.5v v dd = -10v i d = -3.0a i g = 1.0ma -2030nc q g(-2.5) total gate charge at -2.5v v gs = 0v to -2.5v - 12 18 nc q gs gate to source gate charge - 3.0 - nc q gd gate to drain ?miller? charge - 3.8 - nc t on turn-on time v dd = -10v, i d = -3.0a v gs = -4.5v, r gs = 6.8 ? - - 81 ns t d(on) turn-on delay time - 9 - ns t r rise time - 46 - ns t d(off) turn-off delay time - 134 - ns t f fall time - 71 - ns t off turn-off time - - 308 ns v sd source to drain diode voltage i sd = -6.8a - -0.9 -1.2 v t rr reverse recovery time i sd = -3.0a, di sd /dt = 100a/ s- -28ns q rr reverse recovered charge i sd = -3.0a, di sd /dt = 100a/ s- -20nc
?2004 fairchild semiconductor corporation fdm606p rev. d2 fdm606p typical characteristic t a = 25c unless otherwise noted figure 1. normalized power dissipation vs ambient temperature figure 2. maximum continuous drain current vs case temperature figure 3. normalized maximum transient thermal impedance figure 4. peak current capability t a , ambient temperature ( o c) power dissipation multiplier 0 0255075100 150 0.2 0.4 0.6 0.8 1.0 1.2 125 0 2 4 6 8 25 50 75 100 125 150 -i d , drain current (a) t a , case temperature ( o c) v gs = -4.5v v gs = -2.5v 0.01 0.1 1 10 -4 10 -3 10 -2 10 -1 10 0 10 1 10 2 10 3 10 -5 2 t, rectangular pulse duration (s) z ja , normalized thermal impedance notes: duty factor: d = t 1 /t 2 peak t j = p dm x z ja x r ja + t a p dm t 1 t 2 0.5 0.2 0.1 0.05 0.01 0.02 duty cycle - descending order 10 100 200 5 10 -5 10 -4 10 -3 10 -2 10 -1 10 0 10 1 10 3 10 2 -i dm , peak current (a) t, pulse width (s) transconductance may limit current in this region v gs = -2.5v t a = 25 o c i = i 25 150 - t a 125 for temperatures above 25 o c derate peak current as follows: v gs = -4.5v
?2004 fairchild semiconductor corporation fdm606p rev. d2 fdm606p figure 5. transfer characteristics figure 6. saturation characteristics figure 7. drain to source on resistance vs gate voltage and drain current figure 8. normalized drain to source on resistance vs junction temperature figure 9. normalized gate threshold voltage vs junction temperature figure 10. normalized drain to source breakdown voltage vs junction temperature typical characteristic (continued) t a = 25c unless otherwise noted 0 4 8 12 16 20 1.0 1.5 2.0 2.5 -i d , drain current (a) -v gs , gate to source voltage (v) pulse duration = 80 s duty cycle = 0.5% max v dd = 15v t j = 150 o c t j = 25 o c t j = -55 o c 0 4 8 12 16 20 00.51.01.52.0 -i d , drain current (a) -v ds , drain to source voltage (v) v gs = -2.5v pulse duration = 80 s duty cycle = 0.5% max v gs = -2v t a = 25 o c v gs = -4.5v v gs = -1.8v 20 30 40 50 123456 60 i d = -1a -v gs , gate to source voltage (v) i d = -6.8a r ds(on) , drain to source on resistance (m ? ) pulse duration = 80 s duty cycle = 0.5% max 0.75 1.00 1.25 1.50 -80 -40 0 40 80 120 160 normalized drain to source t j , junction temperature ( o c) on resistance v gs = -4.5v, i d = -6.8a pulse duration = 80 s duty cycle = 0.5% max 0.50 0.75 1.00 1.25 -80 -40 0 40 80 120 160 normalized gate t j , junction temperature ( o c) v gs = v ds , i d = 250 a threshold voltage 0.90 0.95 1.00 1.05 1.10 -80 -40 0 40 80 120 160 t j , junction temperature ( o c) normalized drain to source i d = 250 a breakdown voltage
?2004 fairchild semiconductor corporation fdm606p rev. d2 fdm606p figure 11. capacitance vs drain to source voltage figure 12. gate charge waveforms for constant gate currents figure 13. switching time vs gate resistance typical characteristic (continued) t a = 25c unless otherwise noted 100 1000 0.1 1 10 20 4000 c, capacitance (pf) -v ds , drain to source voltage (v) v gs = 0v, f = 1mhz c iss = c gs + c gd c oss ? c ds + c gd c rss = c gd 0 2 4 6 0 6 12 18 24 -v gs , gate to source voltage (v) q g , gate charge (nc) v dd = -10v i d = -6.8a i d = -1a waveforms in descending order: 0 100 200 300 400 0 1020304050 switching time (ns) r gs , gate to source resistance ( ? ) v gs = -4.5v, v dd = -10v, i d = -3.0a t d(off) t r t d(on) t f
?2004 fairchild semiconductor corporation fdm606p rev. d2 fdm606p test circuits and waveforms figure 14. gate charge test circuit figure 15. gate charge waveforms figure 16. switching time test circuit figure 17. switching time waveforms r l v gs + - v ds v dd dut i g(ref) v dd q g(-2.5) v gs = -2.5v q g(tot) v gs = -4.5v v ds -v gs i g(ref) 0 0 q gs q gd r gs r l dut -v gs 0v + - v gs v ds t d(on) t r 90% 10% v ds 90% t f t d(off) t off 90% 50% 50% 10% pulse width v gs t on 10% 0 0
?2004 fairchild semiconductor corporation fdm606p rev. d2 fdm606p thermal resistance vs. mounting pad area the maximum rated junction temperature, t jm , and the thermal resistance of the heat dissipating path determines the maximum allowable device power dissipation, p dm , in an application. therefore the application?s ambient temperature, t a ( o c), and thermal resistance r ja ( o c/w) must be reviewed to ensure that t jm is never exceeded. equation 1 mathematically represents the relationship and serves as the basis for establishing the rating of the part. in using surface mount devices such as the microfet package, the environment in which it is applied will have a significant influence on the part?s current and maximum power dissipation ratings. precise determination of p dm is complex and influenced by many factors: 1. mounting pad area onto which the device is attached and whether there is copper on one side or both sides of the board. 2. the number of copper layers and the thickness of the board. 3. the use of external heat sinks. 4. the use of thermal vias. 5. air flow and board orientation. 6. for non steady state applications, the pulse width, the duty cycle and the transient thermal response of the part, the board and the environment they are in. fairchild provides thermal information to assist the designer?s preliminary application evaluation. figure 18 defines the r ja for the device as a function of the top copper (component side) area. this is for a horizontally positioned fr-4 board with 1oz copper after 1000 seconds of steady state power with no air flow. this graph provides the necessary information for calculation of the steady state junction temperature or power dissipation. pulse applications can be evaluated using the fairchild device spice thermal model or manually utilizing the normalized maximum transient thermal impedance curve. thermal resistances corresponding to other copper areas can be obtained from figure 18 or by calculation using equation 2. the area, in square inches is the top copper area including the gate and source pads. (eq. 1) p dm t jm t a ? () z ja ----------------------------- = (eq. 2) r ja 58.9 6.8 0.041 area + () ------------------------------------- + = 50 100 150 200 250 0.001 0.01 0.1 1 10 figure 18. thermal resistance vs mounting pad area r ja = 58.9 + 6.8/(0.041+area) r ja ( o c/w) area, top copper area (in 2 )
?2004 fairchild semiconductor corporation fdm606p rev. d2 fdm606p pspice electrical model .subckt fdm606p 2 1 3 ; rev oct. 2001 ca 12 8 18.3e-10 cb 15 14 18.3e-10 cin 6 8 19.8e-10 dbody 5 7 dbodymod dbreak 7 11 dbreakmod dplcap 10 6 dplcapmod ebreak 5 11 17 18 -23.4 eds 14 8 5 8 1 egs 13 8 6 8 1 esg 5 10 8 6 1 evthres 6 21 19 8 1 evtemp 6 20 18 22 1 it 8 17 1 ldrain 2 5 1e-9 lgate 1 9 1.1e-9 lsource 3 7 0.78e-9 mmed 16 6 8 8 mmedmod mstro 16 6 8 8 mstromod mweak 16 21 8 8 mweakmod rbreak 17 18 rbreakmod 1 rdrain 50 16 rdrainmod 8.5e-3 rgate 9 20 16 rldrain 2 5 10 rlgate 1 9 11 rlsource 3 7 7.8 rslc1 5 51 rslcmod 1e-6 rslc2 5 50 1e3 rsource 8 7 rsourcemod 11e-3 rvthres 22 8 rvthresmod 1 rvtemp 18 19 rvtempmod 1 s1a 6 12 13 8 s1amod s1b 13 12 13 8 s1bmod s2a 6 15 14 13 s2amod s2b 13 15 14 13 s2bmod vbat 22 19 dc 1 eslc 51 50 value={(v(5,51)/abs(v(5,51)))*(pwr(v(5,51)/(1e-6*97),2.5))} .model dbodymod d (is = 8e-11 n=1.07 rs = 1.3e-2 trs1 = 1e-3 trs2 = 1e-6 xti=0 ikf=0.2 cjo = 5.9e-10 tt = 14.5e-9 m = 0.47) .model dbreakmod d (rs = 5.3e-1 trs1 = 5.5e-3 trs2 = -9e-5) .model dplcapmod d (cjo = 9.4e-10 is = 1e-30 n = 10 m = 0.73) .model mmedmod pmos (vto = -0.96 kp = 1.3 is=1e-30 n = 10 tox = 1 l = 1u w = 1u rg = 16) .model mstromod pmos (vto = -1.22 kp = 54 is = 1e-30 n = 10 tox = 1 l = 1u w = 1u) .model mweakmod pmos (vto = -0.8 kp = 0.05 is = 1e-30 n = 10 tox = 1 l = 1u w = 1u rg = 160 rs = 0.1) .model rbreakmod res (tc1 = 7e-4 tc2 = -1e-7) .model rdrainmod res (tc1 = 1.5e-3 tc2 = 4.9e-6) .model rslcmod res (tc1 = 3.7e-3 tc2 = 7.8e-6) .model rsourcemod res (tc1 = 3e-3 tc2 = 5.2e-6) .model rvthresmod res (tc1 = 1.2e-3 tc2 = 1.2e-6) .model rvtempmod res (tc1 = -6.4e-4 tc2 = -1e-9) .model s1amod vswitch (ron = 1e-5 roff = 0.1 von = 3.0 voff= 1.0) .model s1bmod vswitch (ron = 1e-5 roff = 0.1 von = 1.0 voff= 3.0) .model s2amod vswitch (ron = 1e-5 roff = 0.1 von = 0.5 voff= -0.3) .model s2bmod vswitch (ron = 1e-5 roff = 0.1 von = -0.3 voff= 0.5) .ends note: for further discussion of the pspice model, consult a new pspice sub-circuit for the power mosfet featuring global temperature options ; ieee power electronics specialist conference records, 1991, written by william j. hepp and c. frank wheatley. 1 gate rgate evtemp 18 22 9 + 12 13 8 14 13 13 15 s1a s1b s2a s2b ca cb egs eds cin mweak rdrain dbreak ebreak dbody drain rsource source rbreak rvtemp vbat it evthres esg dplcap eslc rslc1 rslc2 6 8 6 10 5 51 50 5 51 16 21 11 8 14 5 8 6 8 7 3 17 18 19 2 + + + + + + + 19 8 22 mmed mstro rvthres lsource rlsource ldrain rldrain lgate rlgate 20 8 17 18
?2004 fairchild semiconductor corporation fdm606p rev. d2 fdm606p saber electrical model rev october 2001 template fdm606p n2,n1,n3 electrical n2,n1,n3 { var i iscl dp..model dbodymod = (isl = 8.0e-11, nl=1.07, rs = 1.3e-2, trs1 = 1e-3, trs2 = 1e-6, xti=0, cjo = 5.9e-10, ikf=0.2, tt = 14.5e -9, m = 0.47) dp..model dbreakmod = (rs = 5.3e-1, trs1 = 5.5e-3, trs2 = -9.0e-5) dp..model dplcapmod = (cjo = 9.4e-10, isl=10e-30, nl=10, m=0.73) m..model mmedmod = (type=_p, vto = -0.96, kp=1.3, is=1e-30, tox=1) m..model mstrongmod = (type=_p, vto = -1.22, kp = 54, is = 1e-30, tox = 1) m..model mweakmod = (type=_p, vto = -0.8, kp = 0.05, is = 1e-30, tox = 1, rs=0.1) sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = 3.0, voff = 1.0) sw_vcsp..model s1bmod = (ron = 1e-5, roff = 0.1, von = 1.0, voff = 3.0) sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = 0.5, voff = -0.3) sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = -0.3, voff = 0.5) c.ca n12 n8 = 18.3e-10 c.cb n15 n14 = 18.3e-10 c.cin n6 n8 = 19.8e-10 dp.dbody n5 n7 = model=dbodymod dp.dbreak n7 n11 = model=dbreakmod dp.dplcap n10 n6 = model=dplcapmod i.it n8 n17 = 1 l.ldrain n2 n5 = 1e-9 l.lgate n1 n9 = 1.1e-9 l.lsource n3 n7 = 0.78e-9 m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u res.rbreak n17 n18 = 1, tc1 = 7e-4, tc2 = -1e-7 res.rdrain n50 n16 = 8.5e-3, tc1 = 1.5e-3, tc2 = 4.9e-6 res.rgate n9 n20 = 16 res.rldrain n2 n5 = 10 res.rlgate n1 n9 = 11 res.rlsource n3 n7 = 7.8 res.rslc1 n5 n51= 1e-6, tc1 = 3.7e-3, tc2 =7.8e-6 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 11e-3, tc1 = 3e-3, tc2 =5.2e-6 res.rvtemp n18 n19 = 1, tc1 = -6.4e-4, tc2 = -1e-9 res.rvthres n22 n8 = 1, tc1 = 1.2e-3, tc2 = 1.2e-6 spe.ebreak n5 n11 n17 n18 = -23.4 spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n5 n10 n6 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 spe.evthres n6 n21 n19 n8 = 1 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc=1 equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/97))** 2.5)) } } 1 gate rgate evtemp 18 22 9 + 12 13 8 14 13 13 15 s1a s1b s2a s2b ca cb egs eds cin mweak rdrain dbreak ebreak dbody drain rsource source rbreak rvtemp vbat it evthres esg dplcap iscl rslc1 rslc2 6 8 6 10 5 51 50 16 21 11 8 14 5 8 6 8 7 3 17 18 19 2 + + + + + + 19 8 22 mmed mstro rvthres lsource rlsource ldrain rldrain lgate rlgate 20 8 17 18
?2004 fairchild semiconductor corporation fdm606p rev. d2 fdm606p spice thermal model rev october 2001 fdm606p_ja junction ambient copper area= 1sq.in ctherm1 junction c2 2e-4 ctherm2 c2 c3 3.0e-4 ctherm3 c3 c4 7.0e-4 ctherm4 c4 c5 2.0e-3 ctherm5 c5 c6 6.4e-3 ctherm6 c6 c7 3.0e-2 ctherm7 c7 c8 2.8e-1 ctherm8 c8 ambient 2.9 rtherm1 junction c2 1.0 rtherm2 c2 c3 1.3 rtherm3 c3 c4 2.5 rtherm4 c4 c5 3.0 rtherm5 c5 c6 4.0 rtherm6 c6 c7 7.7 rtherm7 c7 c8 12.7 rtherm8 c8 ambient 24 saber thermal model saber thermal model fdm606p copper area= 1sq.in template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th c2 = 2.0e-4 ctherm.ctherm2 c2 c3 = 3.0e-4 ctherm.ctherm3 c3 c4 = 7.0e-4 ctherm.ctherm4 c4 c5 = 2.0e-3 ctherm.ctherm5 c5 c6 = 6.4e-3 ctherm.ctherm6 c6 c7 = 3.0e-2 ctherm.ctherm7 c7 c8 = 2.8e-1 ctherm.ctherm8 c8 tl = 2.9 rtherm.rtherm1 th c2 = 1.0 rtherm.rtherm2 c2 c3 = 1.3 rtherm.rtherm3 c3 c4 = 2.5 rtherm.rtherm4 c4 c5 = 3.0 rtherm.rtherm5 c5 c6 = 4.0 rtherm.rtherm6 c6 c7 = 7.7 rtherm.rtherm7 c7 c8 = 12.7 rtherm.rtherm8 c8 tl = 24 } rtherm6 rtherm8 rtherm7 rtherm5 rtherm4 rtherm3 ctherm4 ctherm6 ctherm5 ctherm3 ctherm2 ctherm1 tl 2 3 4 5 6 7 junction ambient 8 th rtherm2 rtherm1 ctherm7 ctherm8
?2004 fairchild semiconductor corporation fdm606p rev. d2 fdm606p microfet 3x2-8 surface mount jedec microfet 3x2-8 plastic package microfet 3x2-8 8mm tape reel symbol millimeters notes min max a0.801.001 a1 0.00 0.05 1 a2 0.65 0.75 1 a3 0.15 0.25 1 b0.120.281 b1 0.24 0.50 1 d2.903.101 e1.902.101 d2 0.46 0.61 1 e2 0.45 0.60 1 d3 0.91 1.02 1 e3 0.15 0.35 1 e0.65 bsc1 l0.210.371 l2 0.00 0.10 1 l3 0.00 0.10 1 n84 r 0.127 bsc 1 r1 0.127 bsc 1 ? 0 o 12 o notes: 1. all dimensions are in mm. 2. package outline exclusive of mold flash & metal burr. 3. package outine inclusive of plating. 4. n is the total number of terminals. 5. package surface finishing of ra 0.4 um max. user direction of feed 2.0mm 1.77mm 3.5mm 1.5mm dia. hole 8.0mm 4.0mm cover tape 17.0mm 13.0mm 60.0mm 13.0mm 178mm general information 1. 3000 pieces per reel 2. order in multiples of full reels only. 3. meets eia-481 revision ?a? specifications. 4.0mm eb 1 2 3 4 56 7 8 b1 d3 d2 e2 e3 exposed l2 1234 5 6 7 8 l3 d 4x btm mold package top mold package e radius r1 detail ?a? 4x a a2 a3 a1 pad l 3.51 1.91 0.71 0.83 (0.65) 0.57 0.3 1.19 0.36 typ 0.65 typ detail ?a? r recommended land pattern 1 8 2.50
disclaimer fairchild semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function or design. fairchild does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. trademarks the following are registered and unregistered trademarks fairchild semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. life support policy fairchild?s products are not authorized for use as critical components in life support devices or systems without the express written approval of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. product status definitions definition of terms datasheet identification product status definition advance information preliminary no identification needed obsolete this datasheet contains the design specifications for product development. specifications may change in any manner without notice. this datasheet contains preliminary data, and supplementary data will be published at a later date. fairchild semiconductor reserves the right to make changes at any time without notice in order to improve design. this datasheet contains final specifications. fairchild semiconductor reserves the right to make changes at any time without notice in order to improve design. this datasheet contains specifications on a product that has been discontinued by fairchild semiconductor. the datasheet is printed for reference information only. formative or in design first production full production not in production isoplanar? littlefet? microcoupler? microfet? micropak? microwire? msx? msxpro? ocx? ocxpro? optologic ? optoplanar? pacman? pop? fast ? fastr? fps? frfet? globaloptoisolator? gto? hisec? i 2 c? i-lo ? implieddisconnect? rev. i14 acex? activearray? bottomless? coolfet? crossvolt ? dome? ecospark? e 2 cmos? ensigna? fact? fact quiet series? power247? poweredge? powersaver? powertrench ? qfet ? qs? qt optoelectronics? quiet series? rapidconfigure? rapidconnect? serdes? silent switcher ? smart start? spm? stealth? superfet? supersot?-3 supersot?-6 supersot?-8 syncfet? tinylogic ? tinyopto? trutranslation? uhc? ultrafet ? unifet? vcx? across the board. around the world.? the power franchise ? programmable active droop?

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